Shift register

what is shift register

In digital circuits a shift register is a group of flip flops set up in a linear fashion which have their inputs and outputs connected together in such a way that the data is shifted down the line when the circuit is activated

Types of shift register

Shift registers can have a combination of serial and parallel inputs and outputs, including serial-in, parallel-out (SIPO) and parallel-in, serial-out (PISO) types. There are also types that have both serial and parallel input and types with serial and parallel output. There are also bi-directional shift registers which allow you to vary the direction of the shift registers. The serial input and outputs of a register can also be connected together to create a circular shift registers. One could also create multi-dimensional shift registers, which can perform more complex computation.

Bidirectional shift register

Serial in serial out Shift register ( siso shift register )

These are the simplest kind of shift registers . The data string is presented at ‘Data In’, and is shifted right one stage each time ‘Data Advance’ is brought high. At each advance, the bit on the far left (i.e. ‘Data In’) is shifted into the first flip-flop’s output. The bit on the far right (i.e. ‘Data Out’) is shifted out and lost.

The data are stored after each flip-flop on the ‘Q’ output, so there are four storage ‘slots’ available in this arrangement, hence it is a 4-Bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As ‘Data In’ presents 1,1,0,1,0,0,0,0 (in that order, with a pulse at ‘Data Advance’ each time. This is called clocking or strobing) to the register, this is the result. The left hand column corresponds to the left-most flip-flop’s output pin, and so on.

So the serial output of the entire register is 11010000 (). As you can see if we were to continue to input data, we would get exactly what was put in, but offset by four ‘Data Advance’ cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high. This arrangement performs destructive readout – each datum is lost once it been shifted out of the right-most bit.

Non destructive readout

Non-destructive readout can be achieved using the configuration shown below. Another input line is added – the Read/Write Control. When this is high (i.e. write) then the shift registers behaves as normal, advancing the input data one place for every clock cycle, and data can be lost from the end of the register. However, when the R/W control is set low (i.e. read), any data shifted out of the register at the right becomes the next input at the left, and is kept in the system. Therefore, as long as the R/W control is set low, no data can be lost from the system.

Serial in parallel out Shift register ( SIPO Shift register )

This configuration allows conversion from serial to parallel format. Data are input serially, as described in the SISO section above. Once the data has been input, it may be either read off at each output simultaneously, or it can be shifted out and replaced.

Parallel in serial out Shift register ( PISO Shift register )

This configuration has the data input on lines D1 through D4 in parallel format. To write the data to the register, the Write/Shift control line must be held LOW. To shift the data, the W/S control line is brought HIGH and the registers are clocked. The arrangement now acts as a SISO shift registers, with D1 as the Data Input. However, as long as the number of clock cycles is not more than the length of the data-string, the Data Output, Q, will be the parallel data read off in order.

universal shift register

A Universal shift register is a register which has both the right shift and left shift with parallel load capabilities. Universal shift registers are used as memory elements in computers. A Unidirectional shift registers is capable of shifting in only one direction. A bidirectional shift registers is capable of shifting in both the directions. The Universal shift registers is a combination design of bidirectional shift registers and a unidirectional shift registers with parallel load provision.

n-bit universal shift register –
A n-bit universal shift registers consists of n flip-flops and n 4×1 multiplexers. All the n multiplexers share the same select lines(S1 and S0)to select the mode in which the shift registers operates. The select inputs select the suitable input for the flip-flops.

Basic connections –

1. The first input (zeroth pin of multiplexer) is connected to the output pin of the corresponding flip-flop.
2. The second input (first pin of multiplexer) is connected to the output of the very-previous flip flop which facilitates the right shift.
3. The third input (second pin of multiplexer) is connected to the output of the very-next flip-flop which facilitates the left shift.
4. The fourth input (third pin of multiplexer) is connected to the individual bits of the input data which facilitates parallel loading.