Classification of memories
Table of Contents
Classification of memory, ROM, RAM
The important common element of the memories we will study is that they are random access memories, or RAM. This means that each bit of information can be individually stored or retrieved | with a valid input address. This is to be contrasted with sequential memories in which bits must be stored or retrieved in a particular sequence, for example with data storage on magnetic tape. Unfortunately the term RAM has come to have a more specific meaning: A memory for which bits can both be easily stored or retrieved (\written to” or \read from”).
Classification of memories
In general, refers to random access memory. All of the devices we are considering to be \memories” (RAM, ROM, etc.) are random access. The term RAM has also come to mean memory which can be both easily written to and read from.
There are two main technologies used for RAM:
1.) Static RAM
These essentially are arrays of flip-flops. They can be fabricated in ICs as large arrays of tint flip-flops.) \SRAM” is intrinsically somewhat faster than dynamic RAM.
2.) Dynamic RAM
Uses capacitor arrays. Charge put on a capacitor will produce a HIGH bit if its voltage V = Q=C exceeds the threshold for the logic standard in use. Since the charge will \leak” o_ through the resistance of the connections in times of order _ 1 msec, the stored information must be continuously refreshed (hence the term \dynamic”). Dynamic RAM can be fabricated with more bits per unit area in an IC than static RAM. Hence, it is usually the technology of choice for most large-scale IC memories.
ROM ( Read only memory )
Information cannot be easily stored. The idea is that bits are initially denned and are never changed thereafter. As an example, it is generally prudent for the instructions used to initialize a computer upon initial power-up to be stored in ROM. The following terms refer to versions of ROM for which the stored bits can be over-written, but not easily.
PROM ( Programmable ROM )
Bits can be set on a programming bench by burning fusible links, or equivalent. This technology is also used for programmable array logic (PALs), which we will briefly discuss in class.
ROM which can be erased using ultraviolet light.
ROM which can be erased electronically.
A few other points of terminology:
As you know, a bit is a binary digit. It represents the smallest element of information.
A byte is 8 bits.
A K of memory is 210 = 1024 bits (sometimes written KB). And a megabit (MB) is
1K _ 1K bits.
RAM is organized into many data \words” of some prescribed length. For example, a RAM which has 8K = 8192 memory locations, with each location storing a data word of \width” 16 bits, would be referred to as a RAM of size 8K _ 16. The total storage capacity of this memory would therefore be 128KB, or simply a \128K” memory. (With modern very large scale integration (VLSI) technology, a typical RAM IC might be 16 MB. Besides the memory \size,” the other important specification for memory is the access time. This is the time delay between when a valid request for stored data is sent to a memory and when the corresponding bit of data appears at the output. A typical access time, depending upon the technology of the memory, might be _ 10 ns.
A circuit for implementing one or more switching functions of several variables was described in the preceding section and illustrated in Figure . The components of the circuit are
- • An n × 2n decoder, with n input lines and 2n output lines
- • One or more OR gates, whose outputs are the circuit outputs
- • An interconnection network between decoder outputs and OR gate inputs
The decoder is an MSI circuit, consisting of 2n n-input AND gates, that produces all the minterms of n variables. It achieves some economy of implementation, because the same decoder can be used for any application involving the same number of variables. What is special to any application is the number of OR gates and the specific outputs of the decoder that become inputs to those OR gates. Whatever else can be done to result in a general-purpose circuit would be most welcome. The most general-purpose approach is to include the maximum number of OR gates, with provision to interconnect all 2n outputs of the decoder with the inputs to every one of the OR gates. Then, for any given application, two things would have to be done:
• The number of OR gates used would be fewer than the maximum number, the others remaining unused.
• Not every decoder output would be connected to all OR gate inputs.This scheme would be terribly wasteful and doesn‘t sound like a good idea. Instead, suppose a smaller number, m, is selected for the number of OR gates to be included, and an interconnection network is set up to interconnect the 2n decoder outputs to the m OR gate inputs. Such a structure is illustrated in Figure 21. It is an LSI combinational circuit with n inputs and m outputs that, for reasons that will become clear shortly, is called a read-only memory (ROM).
A ROM consists of two parts:
• An n × 2n decoder
• A 2n × m array of switching devices that form interconnections between the 2n lines from the decoder and the m output lines The 2n output lines from the decoder are called the word lines. Each of the 2n combinations that constitute the inputs to the interconnection array corresponds to a minterm and specifies an address. The memory consists of those connections that are actually made in the connection matrix between the word lines and the output lines.
Once made, the connections in the memory array are permanent.8 So this memory is not one whose contents can be changed readily from time to time; we ―write‖ into this memory but once. However, it is possible to ―read‖ the information already stored (the connections actually made) as often as desired, by applying input words and observing the output words. That‘s why the circuit is called read-only memory. Before you continue reading, think of two possible ways in which to fabricate a ROM so that one set of connections can be made and another set left unconnected.
Continue reading after you have thought about it.
A ROM can be almost completely fabricated except that none of the connections are made. Such a ROM is said to be blank. Forming the connections for a particular application is called programming the ROM. In the process of programming the ROM, a mask is produced to cover those connections that are not to be made. For this reason, the blank form of the ROM is called mask programmable
A ROM truth table and its program.
Mask programmed ROM
In the case of a mask-programmed ROM, the ROM is programmed at the manufacturer‘s site according to the specifications of the customer. A photographic negative, called a mask, is used to store the required data on the ROM chip. A different mask would be needed for storing each different set
Typical timing diagram a ROM read operation of information. As preparation of a mask is an expensive proposition, mask-programmed ROM is economical only when manufactured in large quantities. The limitation of such a ROM is that, once programmed, it cannot be reprogrammed. The basic storage element is an NPN bipolar transistor, connected in common-collector configuration, or a MOSFET in common drain configuration. Figures 15.16(a) and (b) show a MOSFET-based basic cell connection when storing a ‘1‘ and ‘0‘ respectively. As is clear from the figure, the connection of the ‘row line‘ to the gate of the MOSFET stores ‘1‘ at the location when the ‘row line‘ is set to level ‘1‘.
A floating-gate connection is used to store ‘0‘. The data programmed into the ROM are given in the adjoining truth table. The transistors with an open base store a ‘0‘, whereas those with their bases connected to the corresponding decoder output store a ‘1‘. As an illustration, transistors Q30, Q20, Q10 and Q00 in row 0 store ‘1‘, ‘0‘, ‘1‘ and ‘0‘ respectively. The stored information in a given row is available at the output when the corresponding decoder is enabled, and that ‘row line‘ is set to level ‘1‘. The output of the memory cells appears at the column lines. For example, when the address input is ‘11‘, row 3 is enabled and the data item at the output is 0110.
Basic cell connection of a mask programmed ROM
In the ROM architecture shown in Fig. 15.17, the number of memory cells in a row represents the word size. The four memory cells in a row here constitute a four-bit register. There are four such registers in this ROM. In a 16× 8 ROM of this type there will be 16 rows of such transistor cells, with each row having eight memory cells. The decoder in that case would be a 1-of-16 decoder.
In the case of PROMs, instead of being done at the manufacturer‘s premises during the manufacturing process, the programming is done by the customer with the help of a special gadget called a PROM programmer. Since the data, once programmed, cannot be erased and reprogrammed, these devices are also referred to as one-time programmable ROMs. The basic memory cell of a PROM is similar to that of a mask-programmed ROM. Above show a MOSFET-based memory cell and bipolar memory cell respectively. In the case of a PROM, each of the connections that were left either intact or open in the case of a mask-programmed ROM are made with a thin fusible link, as shown in Fig. 15.18.
The different interconnect technologies used in programmable logic devices are comprehensively covered in Chapter 9. Basic fuse technologies used in PROMs are metal links, silicon links and PN junctions. These fusible links can be selectively blown off to store desired data. A sufficient current is injected through the fusible link to burn it open to store ‘0‘. The programming operation, as said earlier, is done with a PROM programmer. The PROM chip is plugged into the socket meant for the purpose. The programmer circuitry selects each address of the PROM one by one, burns in the required data and then verifies the correctness of the data before proceeding to the next address.
The data are fed to the programmer from a keyboard or a disk drive or from a computer. PROM chips are available in various word sizes and capacities. 27LS19, 27S21, 28L22, 27S15, 24S41, 27S35, 24S81, 27S45, 27S43 and 27S49 are respectively 32× 8, 256× 4, 256× 8, 512× 8, 1K× 4, 1K× 8, 2K× 4, 2K× 8, 4K× 8 and 8K× 8 PROMS. The typical access time in the case of these devices is in the range 50–70 ns. MOS PROMs are available with much greater capacities than bipolar PROMs. Also, the power dissipation is much lower in MOS PROMs than it is in the case of bipolar PROMs with similar capacities
Internal structure of a 4 x 4 bipolar mask programmed ROM
Basic Memory Cell of a PROM
EPROM can be erased and reprogrammed as many times as desired. Once programmed, it is nonvolatile, i.e. it holds the stored data indefinitely. There are two types of EPROM, namely the ultraviolet-erasable PROM (UV EPROM) and electrically erasable PROM (EEPROM). The memory cell in a UV EPROM is a MOS transistor with a floating gate. In the normal condition, the MOS transistor is OFF. It can be turned ON by applying a programming pulse (in the range 10–25 V) that injects electrons into the floating-gate region. These electrons remain trapped in the gate region even after removal of the programming pulse. This keeps the transistor ON once it is programmed to be in that state even after the removal of power.
The stored information can, however, be erased by exposing the chip to ultraviolet radiation through a transparent window on the top of the chip meant for the purpose. The photocurrent thus produced removes the stored charge in the floating-gate region and brings the transistor back to the OFF state. The erasing operation takes around 15– 20 min, and the process erases information on all cells of the chip. It is not possible to carry out any selective erasure of memory cells. Intel‘s 2732 is 4K× 8 UV EPROM hardware implemented with NMOS devices. Type numbers 2764, 27128, 27256 and 27512 have capacities of 8K× 8, 16K× 8, 32K× 8 and 64K× 8 respectively.
The access time is in the range 150–250 ns. UV EPROMs suffer from disadvantages such as the need to remove the chip from the circuit if it is to be reprogrammed, the nonfeasibility of carrying out selective erasure and the reprogramming process taking several tens of minutes. These are overcome in the EEPROMs and flash memories discussed in the following paragraphs. The memory cell of an EEPROM is also a floating-gate MOS structure with the slight modification that there is a thin oxide layer above the drain of the MOS memory cell. Application of a high-voltage programming pulse between gate and drain induces charge in the floating-gate region which can be erased by reversing the polarity of the pulse.
Since the charge transport mechanism requires very low current, erasing and programming operations can be carried out without removing the chip from the circuit. EEPROMs have another advantage – it is possible to erase and rewrite data in the individual bytes in the memory array. The EEPROMs, however, have lower density (bit capacity per square mm of silicon) and higher cost compared with UV EPROMs.
Random Access Memory
RAM has three basic building blocks, namely an array of memory cells arranged in rows and columns with each memory cell capable of storing either a ‘0‘ or a ‘1‘, an address decoder and a read/write control logic. Depending upon the nature of the memory cell used, there are two types of RAM, namely static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, the memory cell is essentially a latch and can store data indefinitely as long as the DC power is supplied. DRAM on the other hand, has a memory cell that stores data in the form of charge on a capacitor. Therefore, DRAM cannot retain data for long and hence needs to be refreshed periodically. SRAM has a higher speed of operation than DRAM but has a
smaller storage capacity.
When a given application requires a RAM or ROM with a capacity that is larger than what is available on a single chip, more than one such chip can be used to achieve the objective. The required enhancement in capacity could be either in terms of increasing the word size or increasing the number of memory locations.
Word Size Expansion
Let us take up the task of expanding the word size of an available 16× 4 RAM chip from four bits to eight bits. Below figure shows a diagram where two such RAM chips have been used to achieve the desired effect. The arrangement is straightforward. Both chips are selected or deselected together. Also, the input that determines whether it is a ‘read‘ or ‘write‘ operation is common to both chips. That is, both chips are selected for ‘read‘ or ‘write‘ operation together. The address inputs to the two chips are also common. The memory locations corresponding to various address inputs store four higher-order bits in the case of RAM-1 and four lower-order bits in the case of RAM-2. In essence, each of the RAM chips stores half of the word. Since the address inputs are common, the same location in each chip is accessed at the same time.
Word size expansion
Memory Location Expansion
Below shows how more than one memory chip can be used to expand the number of memory locations. Let us consider the use of two 16× 8 chips to get a 32× 8 chip. A 32× 8 chip would need five address input lines. Four of the five address inputs, other than the MSB address bit, are common to both 16× 8 chips. The MSB bit feeds the input of one chip directly and the input of the other chip after inversion.
The inputs to the two chips are common. Now, for first half of the memory locations corresponding to address inputs 00000 to 01111 (a total of 16 locations), . The MSB bit of the address is ‘0‘, with the result that RAM-1 is selected and RAM-2 is deselected. For the remaining address inputs of 10000 to 11111 (again, a total of 16 locations), . RAM-1 is deselected while RAM-2 is selected. Thus, the overall arrangement offers a total of 32 locations, 16 provided by RAM-1 and 16 provided by RAM-2. The overall capacity is thus 32× 8.