Power BJT – Construction, Operation and its Characteristics
Table of Contents
Large-area electronics include power transistors. Their properties frequently diverge from those of small-signal devices due to variations in geometry and doping concentrations. In Fig. 26.74, a vertical NPN power transistor’s structure is depicted. The collector terminal is located at the bottom of the device in the power BJT vertical configuration. The cross-sectional area through which the current flows in the device is maximized by this configuration, making it the preferred one. Additionally, the dimensions and doping concentrations differ from those of small switching transistors.
A high base-collector voltage can be applied without causing breakdown because the primary collector region has a low doped impurity concentration. Reduces collector resistance and makes contact with the external collector terminal is another N region with a higher doping concentration. Additionally, the base region is much wider than is typical for small devices. A high base-collector voltage implies that both the collector and base regions are being subjected to relatively high space-charge widths. To prevent punch-through breakdown, a sizable base width is necessary.
Power transistors must also be large-area devices in order to handle large currents.
Power Transistor Characteristics
Large area devices imply a large junction capacitance and, consequently, a lower cutoff frequency for a power transistor compared to a small switching transistor. The relatively wide base width implies a much smaller current gain for power transistors than that of small switching transistors.
Table 26.3 compares two power BJTs’ parameters to those of a general-purpose small signal BJT. In power transistors, the current gain is typically smaller, ranging from 20 to 100, and may be a significant function of temperature and collector current (IC). Fig. 26.75 illustrates typical current gain-collector current characteristics for the 2N3055 power BJT at various temperatures.
The maximum rated collector current lCmax may be related to the highest current that the wires connecting the semiconductor to the external terminals are capable of carrying, the collector current at which the current gain drops below a minimum specified value, or the collector current that causes the greatest amount of power dissipation when the transistor is biased in saturation.
The reverse-biased base-collector junction’s avalanche breakdown is typically linked to a BJT’s maximum rated voltage. The breakdown voltage mechanism in the CE configuration also takes into account the transistor gain in addition to the PN junction breakdown phenomenon. Fig. 26.76 shows typical lC versus VCE characteristics. Before the breakdown voltage is actually reached, IC starts to rise significantly when the transistor is biased to operate in the forward active mode. Once breakdown has taken place, all of the curves have a tendency to merge to the same collector-emitter voltage VCE. The minimum voltage required to keep the transistor from breaking down is VCE sus.
Second breakdown is a breakdown effect that happens when a BJT operates at high voltage and high current. Localized areas of increased heating caused by slight current density inconsistencies lower the semiconductor material’s resistance, which in turn increases the current in those areas. Positive feedback from this effect causes the current to rise further, raising the temperature even more. Eventually, the semiconductor material may actually melt, resulting in a short-circuit between the collector and emitter and a permanent malfunction.
The instantaneous power dissipation in a BJT is given as
The base current is generally much smaller than the collector current; therefore, to a good approximation, the instantaneous power dissipation is
The average power, which is determined by integrating above Eq. (26.27) over one cycle of the signal, is
To guarantee that the temperature of the device stays below a predetermined maximum value, the average power dissipated in a BJT must be kept below a given maximum value. If lC and VCE are taken to be dc values, then at the transistor’s highest rated power PT, we may write
The lC versus VCE characteristics shown in Fig. 26.77 can be used to illustrate the maximum current, voltage, and power limitations. According to Eq. (26.29), the average power limitation PT is a hyperbola. The safe operating area (SOA), which is bounded by IC max, VCE sus, PT, and the transistor’s second breakdown characteristic curve, is the area in which the transistor can be operated safely.
Depending on how far and for how long the Q-point moves outside the area, the iC – vCE operating point may briefly move outside the SOA without harming the transistor. For our purposes, we assume that the device must always be contained within the SOA.
Darlington Pair Configuration
As previously mentioned, a power BJT’s basewidth is relatively wide, resulting in a small current gain. We can increase current gain by using a Darlington pair, as shown in Fig. 26.78. A Darlington pair can be created by physically connecting two discrete transistors or by fabricating the pair on a single chip. The second transistor is driven by the first transistor’s emitter current. Consequently, the overall current gain grows.
Considering the currents, we see that
The overall common-emitter current gain is then
Thus, if the gain of each individual transistor is β1 = β2 =20, then the overall current gain of the Darlington pair is iC/iB = 440. This overall current gain is significantly larger than that of the individual device. A diode may be incorporated, as shown in Fig. 26.78 to assist in turning off the transistor Q2. A reverse current out of the base of transistor Q2 through the diode will pull charge out of the base of this transistor and turn the device off faster than when no diode is used.
When an NPN transistor is required, the Darlington pair depicted in Fig. 26.78 is typically used in the power amplifier’s output stage. It is also possible to use a PNP Darlington pair to increase the power PNP device’s effective current gain. The NPN Darlington pair’s integrated circuit configuration may resemble that shown in Fig. 26.79. The base regions of the two transistors are isolated. Because the SiO2 that is depicted completely penetrates through the P-type base region.