Pentium Processor: Definition, Features & Architecture
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One of the robust members of Intel’s X86 microprocessor family is the Pentium Processor. It is a sophisticated 32-bit superscalar microprocessor that was first released in 1993 and has about 3.1 million transistors. It has a 4 Gb physical memory capacity and a 64-bit data bus and 32-bit address bus. While the range of available clock rates ranges from 60 to 233 MHz.
The Pentium processor’s architectural design is regarded as an improvement over the 80386 and 80486 microprocessors. In essence, Pentium includes changes to the cache structure, data bus width, and numeric coprocessor speed in addition to a dual integer processor. In the case of a Pentium processor, there are two 8K-sized caches: one for data and one for information. A dual integer processor allows for the execution of two instructions per clock cycle. The numeric coprocessor runs at a significantly faster speed than the 80486 numeric coprocessor, and the data bus width in Pentium is 64 bits as opposed to 32 bits in 80386.
However, Pentium Pro, a development over Pentium, is significantly faster than the former. This is due to the architecture’s ability to schedule and execute five simultaneous instructions. It has a level-2 cache that offers 256K-byte size in addition to the level-1 cache, which is 16K-byte like the Pentium. In addition, the Pentium Pro has an error correction component that can detect and correct single-bit errors. The 64 Gb of physically accessible memory provided by the Pentium Pro can be accessed by using an additional four address lines.
Features of Pentium Processor
Following are the features that Pentium processor offers:
- Separate data and instruction caches
- Superscalar architecture
- Execution tracing
- Bus cycle pipelining
- 64-bit data bus
- Dynamic branch prediction
- Internal parity checking
- Performance monitoring
- Dual processing support
What are Superscalar Processors?
Superscalar processors are a distinct class of microprocessors that use an approach known as instruction-level parallelism for the parallel execution of instructions, allowing multiple instructions to be executed in a single clock cycle. It is well-known for being a second-generation RISC processor since these are the ones that run more quickly with smaller instruction sets. The superscalar processor employs the strategy of simultaneously executing two instructions in one clock cycle, in contrast to scalar processors, which can only execute a maximum of one instruction per clock cycle. The superscalar processors complete this task by simultaneously sending a number of instructions to various execution units. As a result, there is high throughput.
Superscalar processors are typically pipelined, it should be noted. However, pipelining differs from super scaling in that pipelining uses a single execution unit that is divided into multiple phases in order to execute multiple instructions as opposed to superscalars, which allow the execution of multiple instructions concurrently using multiple execution units.
Architecture of Pentium Processor
The architectural representation of the Pentium Processor is shown in the following figure:
The various functional units are as follows:
- Bus unit
- Control ROM
- Paging unit
- Prefetch buffer
- Execution unit with two integer pipeline (U-pipe and V-pipe)
- Data cache
- Code cache
- Branch target buffer
- Instruction decode
- Advanced programmable interrupt controller
- Dual processing logic
Let us now understand, how the architectural operation takes place.
The architecture’s bus unit transmits control signals and retrieves data and cade from external memory and IO devices. The external data bus is 64 bits in size, allowing for burst read and burst write-back cycles. The architecture’s paging unit offers optional page size extensions ranging from 2 to 4 Mb. Code cache, branch target buffers, and prefetch buffers work together to load the instructions into the execution unit. The instructions are stored in the external memory or the code cache, from which they are fetched. While the branch target buffer holds the address of the respective branch and the TLB (translational lookaside buffer) within the code cache converts the linear address into the physical address that is used by the code cache.
This processor has two 32-byte prefetch buffer pairs that work together with the branch target buffer. Both buffers work separately, but not simultaneously. Until the branch instruction occurs, one of the prefetch buffers begins to fetch the instructions sequentially. However, as soon as the branch instruction is fetched by the prefetch buffer, BTB will check for the branch. If the branch has not yet happened, however, linear instruction fetching will continue.
On the other hand, if BTB detects the branch while checking, the other prefetch buffer in the pair activates and begins retrieving the instructions from the branch target address. The branching instructions are simultaneously fetched, decoded, and prepared for execution as a result. The U-pipe and V-pipe integer pipelines and respective ALUs are found in the Pentium microprocessor’s execution unit. These pipelines function in five stages: prefetch, decode-1, decode-2, execute, and writeback. All integer and some floating-point instructions must be executed by the U-pipe, whereas simple integer and some floating-point instructions must be executed by the V-pipe.
In this case, the instruction fetch reads each instruction individually and stores them in the instruction queue. The processor does not remain idle while an instruction is being carried out; instead, it checks for the following two instructions in the queue. If the two instructions are independent of one another, then U-pipe and V-pipe are each given a different set of instructions to allow for simultaneous execution. However, if two queued instructions are interdependent, they are both assigned to the U-pipe and executed sequentially while the V-pipe is left idle.
The control ROM, which contains a microcode, is responsible for controlling the Pentium processor’s operations. U-pipe and V-pipe are directly controlled by the control ROM. The 2-way associated set cache is where the processor’s data and code caches are organized. Every cache has 128 sets, each of which consists of 2 lines that are each 32 bytes wide. The cache replacement is handled by the LRU (Least Recently Used) mechanism. As we can clearly see in the above illustration, the prefetch buffer and code cache are connected by a 256 bit bus, allowing 32 bytes of opcode to be buffered in one clock cycle. The data cache has two ports that are used to simultaneously deal with two data references.
An 8259A compatible Advanced Programmable Interrupt Controller that manages interrupts is built into the chip.
The basic Pentium processor model has been covered here, but Intel has also released a number of advanced processors with advanced features in addition to Pentium. Pentium Pro, Pentium II, Pentium III, and Pentium 4 processors are among the different Pentium series.