Monolithic Bi-polar Transistor Construction – 1. Epitaxial growth 2. Oxidation 3. Photolithography 4. Isolation Diffusion 5. Base Diffusion 6. Emitter Diffusion 7. Contact mask 8. Aluminium Metallization 9. Passivation

Monolithic meaning – formed of a single large block of stone. And monolithic meaning in hindi – एक पत्थर का

Monolithic Bi-polar Transistor Construction

The Fabrication of a Monolithic Transistor includes the following steps.

1.        Epitaxial growth

2.        Oxidation

3.        Photolithography

4.        Isolation Diffusion

5.        Base Diffusion

6.        Emitter Diffusion

7.        Contact mask

8.        Aluminium Metallization

9.        Passivation

The letters P and N in the figures refer to type of doping, and a minus (-) or plus (+) with P and N indicates lighter or heavier doping respectively.

1. Epitaxial growth

The creation of the Collector region is the first step in the Fabrication of a Transistor. For the collector current, a low resistivity path is typically required. This is because the collector contact is typically made at the top of the device, Increasing the Device’s VCE(Sat) and collector series resistance.

A technique known as “buried layer” is used to lower the higher collector resistance, as shown in the figure. In this Configuration, the N-type epitaxial layer and P-type substrate are separated by a heavily doped N’region. This submerged N+ layer offers the collector contact C in the active collector region a low resistance path. The buried layer effectively acts as a low resistance shunt path for the current flow.

For Fabricating an NPN Transistor, we begin with a P-type silicon Substrate having a Resistivity of Typically 1Ω-cm, Corresponding to an Acceptor ion Concentration of 1.4 * 10¹⁵ atoms/cm³ . An oxide mask with the necessary pattern for buried layer Diffusion is prepared. This is followed by masking and etching the oxide in the buried layer mask.

Now that it has Diffused into the Substrate, the N-type buried layer. Use of a Slow-diffusing Substance, such as Antimony or arsenic, ensures that the buried layer will remain in place during subsequent diffusions. The sheet Resistivity is Typically around 20 /sq, and the Junction depth is Typically a few microns.

Then, an Epitaxial layer of lightly doped N-silicon is grown on the P-type Substrate by placing the wafer in the furnace at 1200⁰ C and Introducing a gas Containing Phosphorus (donor Impurity). The Resulting structure is shown in figure.

In this Epitaxial layer, the Diffusions that follow are carried out. The thin N-layer Epitaxial layer grown over the P-type Substrate serves as the base for the Formation of all active and passive Components. The most difficult task in processing bi-polar devices is probably getting an Epitaxial layer with the right Thickness and doping with high crystal quality.

2. Oxidation

As shown in figure, a thin layer of silicon dioxide (SiO₂) is grown over the N-type layer by exposing the silicon wafer to an oxygen atmosphere at about 1000⁰ C.

3. Photolithography

In order to remove the SiO2 layer in IC manufacturing, photolithography is primarily used. As depicted in the figure, a thin uniform layer of photosensitive emulsion is first applied to the oxide’s surface (Photo resist). It is covered with the mask, a black-and-white negative of the required pattern. The photo resist beneath the transparent area of the mask becomes poly-merized when exposed to ultraviolet light. Following the removal of the mask, the wafer is chemically treated to dissolve the exposed portions of the photoresist film. The polymerized area is cured to make it corrosion-resistant. After that, the chip is submerged in a hydrofluoric acid etching solution to remove the oxide layer that the polymerized photoresist had failed to shield.

As a result, the SiO2 layer becomes porous, allowing P- or N-type impurities to diffuse through it using the isolation diffusion process as depicted in the figure. After impurities have diffused, sulphuric acid and mechanical abrasion are used to remove the polymerized photoresist.

4. Isolation Diffusion

The integrated circuit contains many devices. Since a number of devices are to be fabricated on the same IC chip, it becomes necessary to provide good isolation between various components and their interconnections.

The most important techniques for isolation are:

1.        PN junction Isolation

2.        Dielectric Isolation

The P+ type impurities are selectively diffused into the N-type epitaxial layer in the PN junction isolation technique until the layer touches the P-type substrate at the bottom. Using this technique, P-type moats encircled N-type isolation regions were produced. Reverse-biased diodes will provide isolation between these islands if the P-substrate is kept at its most negative potential.

The individual components are fabricated inside these islands. This method is very economical, And is the most commonly used isolation method for general purpose integrated circuits.

In the dielectric isolation method, each component is surrounded by a layer of solid dielectric, such as silicon dioxide or ruby, which provides isolation. There is both physical and electrical isolation. Due to the additional processing steps required, this method is very expensive and is typically used to fabricate ICs needed for specialised applications in the aerospace and military.

Figure illustrates the PN junction isolation diffusion method. The procedure is carried out in a furnace with a source of boron. To achieve complete isolation, the diffusion depth must be at least equal to the epitaxial thickness. Device failures are caused by inadequate isolation because all transistors could short to one another. The collector region of the NPN transistor is represented by the N-type island in the figure. The active and passive components that will be formed in the various N-type islands of the epitaxial layer will be isolated in the heavily doped P-type regions denoted P+.

5. Base Diffusion

A crucial step in the creation of a bi-polar transistor is the base’s formation. The base must be positioned so that, during diffusion, neither the isolation region nor the buried layer will come into contact with it. To create diffused resistors for the circuit, the base diffusion step is frequently used in parallel. The diffusion conditions and the size of the opening created during the etching process determine these resistors’ values. The transistor parameters are heavily influenced by the base width. The base junction depth and resistivity must be closely regulated as a result.

The base sheet resistivity should be fairly high (200- 500Ω per square) so that the base does not inject carriers into the emitter. For NPN transistor, the base is diffused in a furnace using a boron source. The diffusion process is done in two steps, pre deposition of dopants at 900⁰ C and driving them in at about 1200⁰ C. The drive-in is done in an oxidizing ambience, so that oxide is grown over the base region for subsequent fabrication steps. Figure shows that P-type base region of the transistor diffused in the N-type island (collector region) using photolithography and isolation diffusion processes.

6. Emitter Diffusion

Emitter Diffusion is the final step in the Fabrication of the Transistor. The emitter opening must lie wholly within the base. Emitter masking not only opens windows for the emitter, but also for the contact point, which provides a low Resistivity ohmic contact path for the emitter Terminal.

Normal heavy N-type emitter Diffusion results in a layer of low Resistivity that can easily inject charge into the base. Commonly, a phosphorus source is used to shorten the diffusion time and prevent the earlier layers from diffusing any further. The emitter is diffused into the base, causing the junction depths to be very close to one another. Thus, a P-region between these two junctions serves as the active base, which can be made extremely narrow by varying the emitter diffusion time. The emitter can be made using a variety of diffusion and drive-in cycles. The emitter’s resistivity is typically not a major factor.

Below is a diagram illustrating how the transistor’s N-type emitter region diffused into the P-type base region. However, the resistivity of the P-type base region itself will serve the purpose of the resistor, negating the need for this step in the fabrication process. This method allows for the simultaneous fabrication of an NPN transistor and a resistor.

7. Contact Mask

After the Fabrication of emitter, windows are etched into the N-type regions where contacts are to be made for Collector and emitter Terminals. Heavily Concentrated Phosphorus N⁺ dopant is Diffused into these regions Simultaneously.

Following are some explanations of why heavy N+ Diffusion is used: When used with silicon, Aluminium, a good Conductor used for Interconnection, is a P-type of Impurity. As a result, it may result in an Undesirable Rectifying or diode contact with the N-material that has been lightly doped. The Si lattice at the surface became Semi-metallic due to the introduction of a high Concentration of N+ dopant. As a result, the N+ layer and the Aluminium layer have an excellent ohmic contact. The Processes of Oxidation, Photolithography, and Isolation Diffusion are used to Accomplish this.

8. Metallization

The active and passive Components of the IC chip are now complete, and the metal leads need to be formed to connect to the device Terminals. The vacuum Deposition method is used to deposit Aluminium all over the wafer. Metal with a single layer has a Thickness of 1 m. As shown in the figure, Metallization is Accomplished by Evaporating Aluminium over the entire surface and then Selectively Removing it to reveal the desired Interconnection and bonding pads.

Metallization is done for making Interconnection between the various Components Fabricated in an IC and Providing bonding pads around the Circumference of the IC chip for later connection of wires

9. Passivation/ Assembly and Packaging

Passivation, which Involves the Deposition of an Insulating and Protective layer over the entire device, comes after Metalization. This Safeguards it from Abrasion and chemical Deterioration during later processing steps. The material of choice for layer Passivation is Typically silicon oxide, silicon nitride, or some combination of these materials, doped or undoped. Chemical vapour Deposition (CVD) is used to deposit the layer at a temperature low enough to protect the Metallization.