Emitter coupled logic (ECL)
Table of Contents
Emitter coupled logic (ECL) , binary to gray code converter
Emitter-coupled logic (ECL) is a non saturated digital logic family. Since transistors do not saturate. it is possible to achieve propagation delays as low as 1-2 ns. This logic family has the lowest propagation delay of any family . And is used mostly in systems requiring very high speed operation. Its noise immunity and power dissipation . however. are the worst of all the logic families available.
A typical basic circuit of the ECL family is shown in Fig . The outputs provide both the OR and NOR functions. Each input is connected to the base of a transistor. The two voltage levels are about – 0.8 V for the high state and about – 1.8 V for the low state. The circuit consists of a differential amplifier. a temperature- and voltage-compensated bias network. And an emitter-follower output. The emitter outputs require a pull-down resistor for current to flow. This is obtained from the input resistor Rp of another similar gate or from an external resistor connected to a negative voltage supply.
The internal temperature- and voltage-compensated bias circuit supplies a reference volt age to the differential amplifier. Bias voltage Vss is set at – 1.3 V . Which is me midpoint of me signal’s logic swing. The diodes in the voltage divider to get ber with Q6. provide a circuit that maintain s a constant VBs value despite changes in temperature or supply voltage. Any one of the power supply inputs could be used as ground. However, the use of the Vcc node as ground and VEE at – 5.2 V results in the best noise immunity.
If any input in the ECL gate is high. The corresponding transistor is tunned OIl and Q5 is turned off . An input of – 0.8 V causes the transistor lO conduct and places -1.6 V OIl the emitters of all of the transistors. (The VB£ drop in EeL transistors is 0.8 V.) Since VBB = – 1.3 V, the base voltage of Q5 is only 0.3 V more positive man its emitter. Q5 is cut off . Because its VBE voltage needs at least 0.6 V to start conducting.
The current in resistor Rc: flows into the base of Q8 (provided that there is a load resistor). This current is so small that only a negligible voltage drop occurs across Rcz-The OR output of the gate is one VBE drop below ground. Or – 0.8 V. which is the high stale. The current flowing through RCI and the conducting transistor causes a drop of about 1 V below ground.The l’\OR output is one VBE drop below this level. or – 1.8 V. which is the low state.
If all inputs are at the low level, all input transistors turn off and Q5 conduct s. The voltage in the common-emitter node is one VBE drop below VBB, or – 2.1 V. Since the base of each input is at a low level of – 1.8 V. each base-emitter junction has only 0.3 V and all input transistors are cut off. RCl draws current thro ugh Q5 that results in a voltage drop of about I V, making the OR output one VBE drop below this. at -1.8 V. or the low level. The current in RCl is negligible and the nor output is one VBE drop below ground, at – 0.8 V. or the high level. This analysis verifies the OR and NOR operations of the circuit.
The propagation delay of the Ee L gale is 2 ns and the power dissipation is 25 mw, giving a speed-power product of 50. which is about the same as that for the Schottky TIL. The noise margin is about 0.3 V and is not as good as that in the TTL gate. High fan-out is possible in the ECl gate because of the high input impedance of the differential amplifier and the low output impedance of the emitter-follower. Because of the extreme high speed of the signals. external wires act like transmission lines. Except for very sha lt wires of a few centimeters .
ECl outputs must use coaxial cables with a resistor termination to reduce line reflection s. The graphic symbol for the ECl gate shown in Fig. 10.18(a). ‘Two outputs are available: one for the NOR function and the other for the OR function. The outputs of two or more ECL gate s can be connected together to form wired logic. As shown in Fig. 1O.18(b), an external wired connection of two NOR outputs produces a wired-OR function. An internal wired connection of two OR outputs is employed in some Eel ICs to produce a wired-AND (sometimes called dot-AND) logic. This property may be utilized when ECL gales are used to form the OR- AND- INVE RT and the OR-AND functions.
Important Short Questions and Answers: Digital Logic Circuits: Number Systems and Digital Logic
1. Convert the hexadecimal number E3FA to binary.
E3FA16 – Hexadecimal E 3 F A
11102 00112 11112 10102
So the equivalent binary value is 11100011111110102
2. Perform the following conversion (1029)10 to gray code ? (decimal to gray code)
1 0 2 9 —– Decimal
0001 0000 0010 1001 —– BCD
0001 0000 0011 1101 —– Gray
Thus the Gray code of 102910 is 00010000001111012
3. Add 1A816 and 67B16
1 A 816
6 7 B16
8 2 316
4. Show the Karnaugh map with the encircled groups for the Boolean function,
F =C’ +A’D’ + A’B’D’ .
- 1 1 1
- 1 1 1
- 1 1
- 1 1 1
5. Perform 2s complement subtraction of 010110-100101.
1’s complement of minuend100101 = 011010
2’s complement of 011010 = 011011
Addition of 010110 + 011011 = 110001
There is no end carry.
Therefore, the answer is –(2’s complement of 110001)
Answer = – 001111
6. Apply Demorgan’s theorems to simplify (A+BC’) ‘.
(A +BC’) ‘ = A’. (BC’) ‘ = A’ . (B’+ C)
7. Plot the expression on K-Map F (w, x, y) =Σ (0,1,3,5,6) + d(2,4).
1 1 1 X
X 1 1
F = x’ +x y’ + w’
8. If A and B are Boolean variables and if A=1 and (A+B) ‘ = 0, find B.
If B=0 (A+B)’=0
If B=1 (A+B)’=0
Hence the value of B= 0 (or) 1 i.e Don’t care
9. What is the feature of gray code (what is gray code) ? What are its applications
The advantage of gray code also called reflected code over pure binary numbers is that a number in gray code changes by only one bit as it proceeds from one number to the next. A typical application of the reflected code occurs . When the analog data are represented . By a continuous change of a shaft position. The shaft is portioned into segments and each segment is assigned a number. If adjacent segment are made to correspond to adjacent reflected-code numbers, ambiguity is reduced, when detection is sensed in the line that separates any two segments.
So in 3-bit code, error may occur due to one bit position, other two bit positions of adjacent sectors are always same and hence there is no possibility of error. Thus in 3-bit code, probability of error is reduced to 66 % and in 4-bit code it is reduced up to 25%.
10. Convert the gray code number 11011 to binary. ( gray code to binary converter )
Solution: gray code
binary code =10010
11. What is even parity?
A parity bit is an extra bit included with a message to make the total number of 1’s either odd or even. If the total number of 1’s is even then . It is called even parity.
12. Find the 2’s complement and 1’s complement of 101101.
1’s complement of 101101 = 010010 2’s complement of 101101 = 010010
13. Simplify X1 +X1 X2.
Solution: x1 + x1x2
14. Find the standard sum for the following function.
f = x1 x2 x3 + x1 x3 x4 + x1 x2 x4.
f = x1 x2 x3 + x1 x3 x4 + x1 x2 x4
= x1 x2 x3(x4+x4’) + x1(x2+x2’) x3x4+x1x2(x3+x3’) x4 = x1x2x3x4 +x1x2x3x4’+x1x2’x3x4 + x1x2x3’x4
15. Convert binary number 11011110 into its decimal equivalent.
- 1 1 0 1 1 1 1 0
- ———– 0 * 20 =0
- ———– 1 * 21=2
- ———– 1 * 22=4
- ———– 1 * 23=8
- ———– 1 * 24=16
- ———– 0 * 25=0
- ———– 1 * 26=64
- ———– 1 * 27=128