## Full Adder, full adder truth table

Table of Contents

Full Adder, full adder truth table, **Truth Table**, Implementation

## Full Adder

The adder known as a “full adder” adds three inputs and generates two outputs. A and B make up the first two inputs, and C-IN is the third input. The normal output is designated as S, which is SUM, and the output carry is designated as C-OUT.

Eight inputs can be combined to form a byte-wide adder using full adders logic, and the carry bit can be cascaded from one adder to the next. We use a full adders because a 1-bit half-adders cannot use a carry-in bit when one is available, so we must use another 1-bit adders. So Three operands are added by a 1-bit full adder, which produces 2-bit results.

**Full Adder Truth Table**

**Logical Expression for SUM:**

Aâ€™ Bâ€™ C-IN + Aâ€™ B C-INâ€™ + A Bâ€™ C-INâ€™ + A B C-IN = C-IN (Aâ€™ Bâ€™ + A B) + C-INâ€™ (Aâ€™ B + A Bâ€™) = C-IN XOR (A XOR B) = (1,2,4,7)

**Logical Expression for C-OUT:**

Aâ€™ B C-IN + A Bâ€™ C-IN + A B C-INâ€™ + A B C-IN = A B + B C-IN + A C-IN = (3,5,6,7)

**Another form in which C-OUT can be implemented:**

A B + A C-IN + B C-IN (A + Aâ€™) = A B C-IN + A B + A C-IN + Aâ€™ B C-IN = A B (1 +C-IN) + A C-IN + Aâ€™ B C-IN = A B + A C-IN + Aâ€™ B C-IN = A B + A C-IN (B + Bâ€™) + Aâ€™ B C-IN = A B C-IN + A B + A Bâ€™ C-IN + Aâ€™ B C-IN = A B (C-IN + 1) + A Bâ€™ C-IN + Aâ€™ B C-IN = A B + A Bâ€™ C-IN + Aâ€™ B C-IN = AB + C-IN (Aâ€™ B + A Bâ€™)

Therefore COUT = AB + C-IN (A EX â€“ OR B)

**Full Adder logic circuit**

#### Implementation of Full Adder using Half Adders

2 Half Adders and an OR gate is required to implement a Full Adder.

So Two bits can be added using this logic circuit, which sends a carry to the next higher order of magnitude and takes a carry from the next lower order of magnitude.

#### Implementation of Full Adder using NAND gates

**Implementation of Full Adder using NOR gates**

Total 9 NOR gates are required to implement a Full Adder.

So One would recognize the logic expressions of a 1-bit half-adder in the logic expression above. Two 1-bit half adders can be cascaded to create a 1-bit full adder.