FET – Field Effect Transistor and its Operation
Table of Contents
FET Full Form – Field Effect Transistor, JFET, MOSFET
Field Effect Transistor
The field effect transistor (FET) is a semiconductor device, which depends for its operation on the control of current by an electric field. There are two type of field effect transistors
1. JFET (Junction Field Effect Transistor)
2. MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
The FET has several advantages over conventional transistor.
1. In a conventional transistor, the operation depends upon the flow of majority and minority carriers. That is why it is called bi-polar transistor. In FET the operation depends upon the flow of majority carriers only. It is called unipolar device.
2. The input to conventional transistor amplifier involves a forward biased PN junction with its inherently low dynamic impedance. The input to FET involves a reverse biased PN junction hence the high input impedance of the order of M-ohm.
3. It is less noisy than a bi-polar transistor.
4. It exhibits no offset voltage at zero drain current.
5. It has thermal stability.
6. It is relatively immune to radiation.
The main disadvantage is its relatively small gain bandwidth product in comparison with conventional transistor.
1. Operation of FET
Consider a sample bar of N-type semiconductor. This is called N-channel and it is electrically equivalent to a resistance as shown in fig. 1.
The external connection is then added by adding ohmic contacts to each side of the channel. Therefore, the current flows through the channel if a voltage is applied across the bar.
The source, denoted by the letter S, is the terminal from which the majority of carriers (electrons) enter the channel. Drain is the name of the terminal, which is identified by the letter D, through which majority carriers exit the channel. Electrons make up the vast majority of carriers in an N-channel device. As a result, the circuit operates as if a dc voltage VDS were applied across a resistance RDS. The drain current ID is the resultant current. VDS and ID rise in tandem as VDS rises.
Now on both sides of the n-type bar heavily doped regions of p-type impurity have been formed by any method for creating pn junction. These impurity regions are called gates (gate1 and gate2) as shown in fig. 2.
Given that both gates are grounded and internally connected, the gate source voltage (VGS = 0) is zero. The term “gate” is used because the current and channel width are controlled by the potential applied between the gate and source.
The reverse biased PN junction forms a depletion region on both of its sides, as is the case with all PN junctions. Only the exposed positive ions on the n side and the exposed negative ions on the p side remain at the junction because the current carriers have diffused across it. With an increase in reverse bias intensity, the depletion region widens. Due to the lack of available current carriers, this channel’s conductivity is typically zero.
Any point along the channel has a different potential depending on how far it is from the drain; in relation to the ground, points closer to the drain have a higher positive potential than points closer to the source. As a result, both depletion regions are exposed to higher reverse voltage close to the drain. Thus, as we approach the drain, the depletion region’s width widens. Now, only a small channel between the no conducting depletion regions can carry electrons from source to drain. This channel’s width affects the resistance between the drain and source.
Now think about how drain current ID and drain source voltage VDS behave. VGS = 0 because there is no voltage at the gate source. Assume that VDS is gradually increased linearly starting at 0V. ID rises as well.
Since the channel behaves as a semiconductor resistance, therefore it follows ohm’s law. The region is called ohmic region, with increasing current, the ohmic voltage drop between the source and the channel region reverse biased the junction, the conducting portion of the channel begins to constrict and ID begins to level off until a specific value of VDS is reached, called the pinch of voltage VP.
At this point, additional increases in VDS don’t lead to an increase in ID. Instead of increasing the cross section as VDS increases, both depletion regions instead move farther into the channel, increasing channel resistance. Because of this, the current is essentially constant and the resistance increases even though the voltage does. This is referred to as the pinch off or saturation region. The IDSS has specified the maximum current that a FET can generate in this region. (Gate shorted; current from drain to source)
As with all pn junctions, when the reverse voltage exceeds a certain level, avalanche breakdown of pn junction occurs and ID rises very rapidly as shown in fig. 3.
Consider now an N-channel JFET with a reverse gate source voltage as shown in fig. 4.
The additional reverse bias, pinch off will occur for smaller values of | VDS |, and the maximum drain current will be smaller. A family of curves for different values of VGS(negative) is shown in fig. 5.
Suppose that VGS= 0 and that due of VDS at a specific point along the channel is +5V with respect to ground. Therefore reverse voltage across either p-n junction is now 5V. If VGS is decreased from 0 to –1V the net reverse bias near the point is 5 – (-1) = 6V. Thus for any fixed value of VDS, the channel width decreases as VGS is made more negative.
ID value changes accordingly as a result. The conducting channel pinches off when the gate voltage is sufficiently negative and the depletion layers come into contact (disappears). The drain current is stopped in this instance. The cut-off gate voltage is denoted by the symbol VGS(off). Similar to pinch off voltage, it is.
There is very little reverse current flowing through the gate source junction because it is a silicon diode that is reverse biased. Gate current ought to be zero. In the end, ID = IS occurs because all of the source’s free electrons move to the drain. The input resistance is extremely high, 10s or 100s of M ohms, because the gate draws almost no reverse current. As a result, JFET is chosen over BJT when a high input impedance is needed. The drawback is that FET requires greater changes in input voltage to produce changes in output current, giving users less control over output current. JFETs have less voltage gain than bi-polar amplifiers as a result.
The transductance curve of a JFET is a graph of output current (ID) vs input voltage (VGS) as shown in fig. 1.
By reading the value of ID and VGS for a particular value of VDS, the transductance curve can be plotted. The transductance curve is a part of parabola. It has an equation of
Data sheet provides only IDSS and VGS(off) value. Using these values the transductance curve can be plotted.